Question 1
- In a computer instruction format, the instruction length is 11 bits and the size of an address fields is 4 bits. Is it possible to have
5 two-address instructions
45 one-address instructions
32 zero-address instructions
Using the specified format? Justify your answer
- Assume that a computer architect has already designed 6 two-address and 24 zero-address instructions using the instruction format above. What is the maximum number of one-address instructions that can be added to the instruction set?
Question 2
Suppose we have the instruction Load 500. Given memory and register R1 contain the values below:
Memory
0x100 | 0x600
...
0x400 | 0x300
...
0x500 | 0x100
...
0x600 | 0x500
...
0x700 | 0x800
R1 | 0x200
Assuming R1 is implied in the indexed addressing mode, determine the actual value loaded into the accumulator and fill in the table below:
Mode, Value Loaded into AC
Immediate,
Direct,
Indirect,
Indexed
Question 3
A nonpiplined system takes 200ns to process a task. The same task can be processed in a five-segment pipeline with a clock cycle of 40ns. Determine the speedup ratio of the pipeline for 200 tasks. What is the maximum speedup that could be achieved with the pipeline unit over the nonpipelined unit?
Question 4
Suppose a computer using direct mapped cache has 2^32 bytes of byte-addressable main memory and a cache of 1024 blocks, where each cache block contains 32 bytes.
- How many blocks of main memory are there?
- What is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, block, and offset fields?
- To which cache block will the memory address 0x000063FA map?
Question 5
Suppose a computer using fully associative cache has 2^24 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes.
- How many blocks of main memory are there?
- What is the format of a memory address as seen by the cache; that is, what are the sizes of the tag and offset fields?
- To which cache block will the memory address 0x01D872 map?
Question 6
Suppose a byte-addressable computer using set associative cache has 2^21 bytes of main memory and a cache of 64 blocks, where each cache block contains 4 bytes.
- If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?
- If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Question 7
You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set associative cache and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided up into blocks, where each block is represented by a letter. Two blocks equals one frame.
System state: see image.
Given the system state as depicted above, answer the following questions:
- How many bits are in a virtual address for process P? Explain.
- How many bits are in a physical address? Explain.
- Show the address format for virtual address 0x12 (specify field name and size) that would be used by the system to translate to a physical address and then translate this virtual address into the corresponding physical address. (Hint: convert the address to its binary equivalent and divide it into the appropriate fields.) Explain how these fields are used to translate to the corresponding physical address.
- Given virtual address 0x06 converts to physical address 0x36. Show the format for a physical address (specify the field names and sizes) that is used to determine the cache location for this address. Explain how to use this format to determine where physical address 0x36 would be located in cache. (Hint: convert 0x36 to binary and divide it into the appropriate fields.)
- Given virtual address 0x19 is located on virtual page 1, offset 9. Indicate exactly how this address would be translated to its corresponding physical address and how the data would be accessed. Include in your explanation how the TLB, Page Table, Cache and Memory are used.
Question 8
Given a virtual memory system with a TLB, a cache, and a page table. Assume the following:
- A TLB hit requires 5ns
- A cache hit requires 12ns
- A memory reference requires 25ns
- A disk reference requires 200ms (this includes updating the page table, cache, and TLB)
- The TLB hit ratio is 90%
- The cache hit rate is 98%
- The page fault rate is .001%
- On a TLB or cache miss, the time required for access includes a TLB and/or cache update, but the access is not restarted
- On a page fault, the page is fetched from disk, all updates are performed but the access is restarted
- All references are sequential (no overlap, nothing done in parallel)
For each of the following, indicate whether or not it is possible. If so, specify the time required for accessing the requested data.
